A design methodology for performance maintenance of 3D Network-on-Chip with multiplexed Through-Silicon Vias

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Authors

Madipour, Farhad
El-Sayed, M.
Murakami, K.J.
Said, M.

Author ORCID Profiles (clickable)

Degree

Grantor

Date

2015-06

Supervisors

Type

Conference Contribution - Paper in Published Proceedings

Ngā Upoko Tukutuku (Māori subject headings)

Keyword

Network-on-Chip (NoC)
yield
Through-Silicon Vias (TSVs)

ANZSRC Field of Research Code (2020)

Citation

Mehdipour, F., El-Sayed, M., Murakami, K., & Said, M. (2015, June). A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias. ACM (Ed.), Proceedings of the 3rd International Workshop on Many-core Embedded Systems (pp.9-16). 10.1145/2768177.2768178.

Abstract

3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. Though, there are still several challenges in 3D integration technology need to be addressed. It is shown in literature that reducing TSV count has a considerable effect in improving yield. The TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. The TSVBOX introduces some delay to the signals to be multiplexed. In this paper, we analyse the TSVBOX timing requirements and deduce a design methodology for TSVBOX-based 3D Network-on-Chip (NoC) to overcome the TSVBOX speed degradation. Performance comparisons under different traffic patterns are conducted to verify our solution. We show that TSVBOX-based 3D NoC performance is highly dependent on the NoC traffic pattern and in most simulation scenarios we tried, it shows almost the same performance of the conventional 3D NoC.

Publisher

ACM DL (Digital Library)

Link to ePress publication

DOI

DOI:10.1145/2768177.2768178

Copyright holder

ACM DL (Digital Library)

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All rights reserved

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