3D FPGA versus multiple FPGA system : enhanced parallelism in smaller area
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Authors
Nunna, K.C.
Madipour, Farhad
Murakami, K.J.
Madipour, Farhad
Murakami, K.J.
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2014-01
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Conference Contribution - Paper in Published Proceedings
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Keyword
3D FPGA
Through-Silicon Vias (TSVs)
Multi-FPGA System
parallel computing
Through-Silicon Vias (TSVs)
Multi-FPGA System
parallel computing
ANZSRC Field of Research Code (2020)
Citation
Nunna, K C., Mehdipour, F., & Murakami, K. (2014, January). 3D FPGA versus multiple FPGA system: enhanced parallelism in smaller area. ACM (Ed.), AusPDC '14 Proceedings of the Twelfth Australasian Symposium on Parallel and Distributed Computing 152: 37-43.
Abstract
Handling large amounts of data is being limited by bandwidth constraint between processors components and their memory counterparts. Three-dimensional integration (3D) is providing possible solution to handle such critical applications. Especially for running larger designs when implementing on multi-FPGA platform, which can produce huge amount of fine-grain parallelism, for satisfying the speed and reliability needs 3D FPGA can be considered as a close candidate to choose. In this paper we tried to show the benefits of running larger designs on 3D FPGA compared to running on multi-FPGA systems using benchmark simulation. Results showed that a TSV-based 3D FPGA achieved better performance and area results.
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