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dc.contributor.authorSaid, M.
dc.contributor.authorMadipour, Farhad
dc.contributor.authorEl-Sayed, Mohamed
dc.contributor.editorIEEE Xplore
dc.date.accessioned2017-06-21T00:11:41Z
dc.date.available2017-06-21T00:11:41Z
dc.date.issued2014-04
dc.identifier.urihttps://hdl.handle.net/10652/3816
dc.description.abstractOne of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.en_NZ
dc.language.isoenen_NZ
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_NZ
dc.rights[Blind-review copy]en_NZ
dc.subjectThrough-Silicon Vias (TSVs)en_NZ
dc.subjectfabricationen_NZ
dc.subjectmultiplexingen_NZ
dc.subjectsiliconen_NZ
dc.subjectthree-dimensional displaysen_NZ
dc.subjectstressen_NZ
dc.subjectthermal stressesen_NZ
dc.titleKeep-Out-Zone analysis for three-dimensional ICsen_NZ
dc.typeConference Contribution - Paper in Published Proceedingsen_NZ
dc.date.updated2017-05-10T05:37:45Z
dc.rights.holderAuthorsen_NZ
dc.identifier.doiDOI: 10.1109/VLSI-DAT.2014.6834862en_NZ
dc.subject.marsden090604 Microelectronics and Integrated Circuitsen_NZ
dc.identifier.bibliographicCitationSaid, M., Mehdipour, F., & El-Sayed, M. (2014, April). Keep-Out-Zone Analysis for Three-Dimensional ICs. IEEE Xplore (Ed.), VLSI Design, Automation and Test (VLSI-TSA) International Symposium (pp.1-4). 10.1109/VLSI-DAT.2014.6834862.en_NZ
unitec.publication.spage1en_NZ
unitec.publication.lpage4en_NZ
unitec.publication.titleTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Testen_NZ
unitec.conference.title2014 International Symposium on VLSI Design, Automation and Test (VLSI-TSA)en_NZ
unitec.conference.orgInstitute of Electrical and Electronics Engineers (IEEE)en_NZ
unitec.conference.locationHsinchu, Taiwanen_NZ
unitec.conference.sdate2014-04-28
unitec.conference.edate2014-04-30
unitec.peerreviewedyesen_NZ
dc.contributor.affiliationUnitec Institute of Technologyen_NZ
unitec.identifier.roms59473en_NZ
unitec.institution.studyareaConstruction + Engineering


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