Keep-Out-Zone analysis for three-dimensional ICs
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Other Title
Authors
Said, M.
Madipour, Farhad
El-Sayed, Mohamed
Madipour, Farhad
El-Sayed, Mohamed
Author ORCID Profiles (clickable)
Degree
Grantor
Date
2014-04
Supervisors
Type
Conference Contribution - Paper in Published Proceedings
Ngā Upoko Tukutuku (Māori subject headings)
Keyword
Through-Silicon Vias (TSVs)
fabrication
multiplexing
silicon
three-dimensional displays
stress
thermal stresses
fabrication
multiplexing
silicon
three-dimensional displays
stress
thermal stresses
ANZSRC Field of Research Code (2020)
Citation
Said, M., Mehdipour, F., & El-Sayed, M. (2014, April). Keep-Out-Zone Analysis for Three-Dimensional ICs. IEEE Xplore (Ed.), VLSI Design, Automation and Test (VLSI-TSA) International Symposium (pp.1-4). 10.1109/VLSI-DAT.2014.6834862.
Abstract
One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Permanent link
Link to ePress publication
DOI
DOI: 10.1109/VLSI-DAT.2014.6834862
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Authors
Copyright notice
[Blind-review copy]