A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Loading...
Thumbnail Image
Other Title
Authors
Said, M.
Shalaby, A.
Madipour, Farhad
Morteza, B.
El-Sayed, M.
Author ORCID Profiles (clickable)
Degree
Grantor
Date
2016
Supervisors
Type
Journal Article
Ngā Upoko Tukutuku (Māori subject headings)
Keyword
3D Network-on-Chip
fabrication
Through-Silicon Vias (TSVs)
ANZSRC Field of Research Code (2020)
Citation
Said, M., Shalaby, A., Mehdipour, F., Morteza, B., & El-Sayed, M. (2016). A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias. Microprocessors and Microsystems, 43, pp.26-46. doi:10.1016/j.micpro.2016.01.011
Abstract
The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOX-based 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patterns
Publisher
Elsevier
Link to ePress publication
DOI
Copyright holder
Elsevier
Copyright notice
All rights reserved
Copyright license