• Login
    View Item 
    •   Research Bank Home
    • Unitec Institute of Technology
    • Study Areas
    • Construction + Engineering
    • Construction + Engineering Journal Articles
    • View Item
    •   Research Bank Home
    • Unitec Institute of Technology
    • Study Areas
    • Construction + Engineering
    • Construction + Engineering Journal Articles
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

    Said, M.; Shalaby, A.; Madipour, Farhad; Morteza, B.; El-Sayed, M.

    Thumbnail
    Share
    View fulltext online
    MES2015ExtendedPaper_ElseiverMICPRO_RevisedVersion.pdf (3.413Mb)
    Date
    2016
    Citation:
    Said, M., Shalaby, A., Mehdipour, F., Morteza, B., & El-Sayed, M. (2016). A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias. Microprocessors and Microsystems, 43, pp.26-46. doi:10.1016/j.micpro.2016.01.011
    Permanent link to Research Bank record:
    https://hdl.handle.net/10652/3758
    Abstract
    The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOX-based 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patterns
    Keywords:
    3D Network-on-Chip, fabrication, Through-Silicon Vias (TSVs)
    ANZSRC Field of Research:
    090604 Microelectronics and Integrated Circuits
    Copyright Holder:
    Elsevier

    Copyright Notice:
    All rights reserved
    Available Online at:
    http://www.sciencedirect.com/science/article/pii/S0141933116000156
    Rights:
    This digital work is protected by copyright. It may be consulted by you, provided you comply with the provisions of the Act and the following conditions of use. These documents or images may be used for research or private study purposes. Whether they can be used for any other purpose depends upon the Copyright Notice above. You will recognise the author's and publishers rights and give due acknowledgement where appropriate.
    Metadata
    Show detailed record
    This item appears in
    • Construction + Engineering Journal Articles [63]

    Te Pūkenga

    Research Bank is part of Te Pūkenga - New Zealand Institute of Skills and Technology

    • About Te Pūkenga
    • Privacy Notice

    Copyright ©2022 Te Pūkenga

    Usage

    Downloads, last 12 months
    54
     
     

    Usage Statistics

    For this itemFor the Research Bank

    Share

    About

    About Research BankContact us

    Help for authors  

    How to add research

    Register for updates  

    LoginRegister

    Browse Research Bank  

    EverywhereInstitutionsStudy AreaAuthorDateSubjectTitleType of researchSupervisorCollaboratorThis CollectionStudy AreaAuthorDateSubjectTitleType of researchSupervisorCollaborator

    Te Pūkenga

    Research Bank is part of Te Pūkenga - New Zealand Institute of Skills and Technology

    • About Te Pūkenga
    • Privacy Notice

    Copyright ©2022 Te Pūkenga